verilog multiple conditional assignment

Verilog Conditional Operator

Just what the heck is that question mark doing.

Have you ever come across a strange looking piece of Verilog code that has a question mark in the middle of it? A question mark in the middle of a line of code looks so bizarre; they’re supposed to go at the end of sentences! However in Verilog the ? operator is a very useful one, but it does take a bit of getting used to.

The question mark is known in Verilog as a conditional operator though in other programming languages it also is referred to as a ternary operator , an inline if , or a ternary if . It is used as a short-hand way to write a conditional expression in Verilog (rather than using if/else statements). Let’s look at how it is used:

Here, condition is the check that the code is performing. This condition might be things like, “Is the value in A greater than the value in B?” or “Is A=1?”. Depending on if this condition evaluates to true, the first expression is chosen. If the condition evaluates to false, the part after the colon is chosen. I wrote an example of this. The code below is really elegant stuff. The way I look at the question mark operator is I say to myself, “Tell me about the value in r_Check. If it’s true, then return “HI THERE” if it’s false, then return “POTATO”. You can also use the conditional operator to assign signals , as shown with the signal w_Test1 in the example below. Assigning signals with the conditional operator is useful!

Nested Conditional Operators

There are examples in which it might be useful to combine two or more conditional operators in a single assignment. Consider the truth table below. The truth table shows a 2-input truth table. You need to know the value of both r_Sel[1] and r_Sel[0] to determine the value of the output w_Out. This could be achieved with a bunch of if-else if-else if combinations, or a case statement, but it’s much cleaner and simpler to use the conditional operator to achieve the same goal.

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?: conditional operator in Verilog

Compact conditional operators.

Many Verilog designs make use of a compact conditional operator:

A comman example, shown below, is an “enable” mask. Suppose there is some internal signal named a . When enabled by en== 1 , the module assigns q = a , otherwise it assigns q = 0 :

The syntax is also permitted in always blocks:

Assigned Tasks

This assignment uses only a testbench simulation, with no module to implement. Open the file src/testbench.v and examine how it is organized. It uses the conditional operator in an always block to assign q = a^b (XOR) when enabled, else q= 0 .

Run make simulate to test the operation. Verify that the console output is correct. Then modify the testbench to use an assign statement instead of an always block . Change the type of q as appropriate for the assign statement.

Turn in your work using git :

Indicate on Canvas that your assignment is done.

Verilog Conditional Statements Tutorial

Conditional statements are crucial in Verilog as they enable you to make decisions and create conditional behaviors in your designs. They allow you to execute specific blocks of code based on certain conditions. In this tutorial, we will explore different types of conditional statements in Verilog and learn how to use them effectively.

Introduction to Conditional Statements

Conditional statements in Verilog provide a way to control the flow of your code based on certain conditions. They are essential for implementing decision-making logic and creating complex behaviors in digital designs. The three primary conditional statements in Verilog are if , else if , and case .

Verilog if Statement

The if statement is used to check a single condition and execute a block of code if the condition evaluates to true. If the condition is false, the code inside the if block is skipped. The syntax of the if statement is as follows:

Verilog else if Statement

The else if statement allows you to check additional conditions if the previous conditions in the if and else if blocks are false. The code inside the first matching condition block is executed, and the rest are skipped. The syntax of the else if statement is as follows:

Verilog case Statement

The case statement is used to perform multi-way decisions based on the value of an expression. It is similar to the switch-case statement in many programming languages. The syntax of the case statement is as follows:

Common Mistakes with Verilog Conditional Statements

• Using blocking assignments inside the conditional blocks, leading to incorrect behavior.
• Not considering all possible cases in the case statement, causing incomplete behavior.
• Mixing different data types in conditionals without proper typecasting.
• Using the assignment operator "=" instead of the equality operator "==" in conditions.
• Overlooking operator precedence in complex conditions, leading to unexpected results.

Frequently Asked Questions (FAQs)

• Q: Can I have nested conditional statements in Verilog? A: Yes, you can nest conditional statements (e.g., if inside else or case inside case ) to create complex decision structures.
• Q: Can I use non-constant expressions in case statements? A: No, Verilog requires constant expressions in case statements, so each case value must be a constant or a constant expression.
• Q: Is the case statement only for sequential logic? A: No, the case statement can be used for both combinational and sequential logic depending on how it is used in the code.
• Q: How does Verilog handle multiple matching cases in a case statement? A: Verilog executes the first matching case it encounters in a case statement and skips the rest.
• Q: Can I use multiple conditions in an if statement? A: Yes, you can use logical operators (e.g., &&, ||) to combine multiple conditions in an if statement.

Conditional statements in Verilog are essential for implementing decision-making logic and creating complex behaviors in digital designs. The if , else if , and case statements enable you to control the flow of your code based on specific conditions. By understanding how to use these conditional statements correctly, you can create efficient and reliable Verilog designs for various applications.

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Conditional Operator (?:)

The conditional operator (?:), also known as the ternary operator, is a unique operator in SystemVerilog that takes three operands: a condition, a value if the condition is true, and a value if the condition is false. It serves as a shorthand way of writing an if-else statement.

The syntax is as follows: condition ? value_if_true : value_if_false .

This operator evaluates the condition first. If the condition is true, the operator returns value_if_true ; otherwise, it returns value_if_false .

Basic Usage

In this example, the value of c will be 20, because the condition a > b is false, so the value of b is assigned to c .

Nested Conditional Operators

You can nest conditional operators to check multiple conditions. Here's an example:

In this example, the value of d will be 20. Here's why: since a > b is false, we move to the second expression (a > c) ? a : c . Since a > c is also false, c is assigned to d .

The conditional operator offers a compact and readable way to express simple conditional logic. However, for more complex conditionals, traditional if-else statements or case statements might be clearer. In the next tutorial, we'll discuss case statements in detail. As always, remember that while these examples provide a simplified introduction, real-world usage can involve much more intricate control flow constructs and combinations.

Potential Pitfalls

Precedence of Operators : The conditional operator has lower precedence than logical and comparison operators, but higher precedence than the assignment operator. This means an expression like a = b > c ? d : e; will behave as a = ((b > c) ? d : e); , not as (a = b) > c ? d : e; .

Type of Operands : The second and third operands (those following the ? and : ) must be of compatible data types. SystemVerilog will not automatically convert one data type to another.

Non-Synthesizable Constructs : In the context of synthesis for hardware, conditional expressions must not perform assignments, and only one of the two result expressions can be evaluated, depending on the condition. For example, something like a > b ? (c = d) : (e = f); is not synthesizable, as it performs an assignment within the expression.

Avoid Complex Nesting : While it's syntactically correct to nest conditional operators, doing so can quickly lead to code that's difficult to read and maintain. For more complex logic, consider using if-else or case statements instead.

Undesired Side Effects : If the second or third operand has a function call or any other operation with a side effect, be aware that only one of them will be evaluated, depending on the condition. The other will not be executed at all, which might not be the expected behavior if you're used to languages where all function arguments are always evaluated.

By being aware of these potential issues, you can use the conditional operator effectively and safely in your SystemVerilog code.

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• The Verilog-AMS Language
• Initial and Always Processes
• Conditional Statements

Conditional Statements 

If statements .

An if statement evaluates an expression and executes the subsequent statement if the expression evaluates to true, otherwise it skips that statement. For example:

An if/else statement evaluates an expression and executes the statement before else if the expression evaluates to true, otherwise it evaluates the statement after the else . For example:

In particular, if sel is a single bit value, the if clause of the above example would be executed if sel were 1, and the else clause would be executed if sel were 0, x , or z .

A common idiom is to nest if/else statements as follows:

In this case an if keyword binds to the next closest else keyword.

Case Statements 

A case statement tests and expression and then enumerates what actions should be taken for the various values that expression can take. For example:

Case statements test using the === operator, so if any of the bits in sel are x or z none of these cases will match and so the case statement will not execute any of its statements. You can associate multiple cases with a single statement by putting the cases in a comma separated list:

It is also possible to specify a default case:

The are two special versions of the case statement available: casez and casex. casex treats an x or a z in either the case expression or the case items as don’t cares whereas casez only treats a z as a don’t care. In addition, ? in literal numbers are also treated as don’t cares:

This example also demonstrates another feature of case statements. Multiple cases may match. They are tried in the order that they are given and the first one that matches is used.

Verilog if-else-if

If without else, if with else, if without else for single statement, if without else for multiple statements, if-else for single statement, if-else for multiple statements.

This conditional statement is used to make a decision on whether the statements within the if block should be executed or not.

• If the expression evaluates to true (i.e. any non-zero value), all statements within that particular if block will be executed
• If it evaluates to false (zero or 'x' or 'z'), the statements inside if block will not be executed
• If there is an else statement and expression is false then statements within the else block will be executed.

If multiple statements need to be placed inside the if or else part, it needs to be enclosed within begin and end .

Hardware Implementation

if without an else part implies that the value remain unchanged for any condition that does not satisfy the expression inside if .

Value of output q is updated whenever d or en changes in value.

Output q will get the value of input d at the positive edge of clock if rstn is high and describes the behavior of a D flop.

Note that the synthesized output indicates a flop with an output q .

In the following example, the design module has a 4-bit output q that is incremented when mode is 1 and decrements when mode is 2 with if else construct. Note that the description does not specify what has to be done if mode is 0 or 3 which are valid values for a 2-bit variable. It is assumed that the circuit does nothing when mode is 1 and 3, but maintain exiting value of q . It is not recommended to leave such ambiguity in real design code, but is shown here to highlight the possibility.

The synthesized output may differ with availability of cells for a given technology library

Shown below is the synthesized output and it is worth to note that q got implemented as a 4-bit flop which has a pin CE to enable the flop. Note that this flop is enabled only when mode is 1 or 2 and not for other values. Output q is fed back through an adder and subtractor block into the input of the same flop through a mux which is again controlled by mode .

Consider the same design from above with a 1-bit mode .

In this case, a regular flop without a CE pin is used along with a few multiplexers to choose the correct signal based on value of mode .

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How to use 2 condition in assign [verilog]

• Thread starter daisordan
• Start date Oct 17, 2012
• Oct 17, 2012

Newbie level 6

always_comb //always_comb is the same function as assign begin if(a==b) z=a; else if (b==c) z=b; end Click to expand...

assign z = (a & b) ? a:z; //I know thats wrong since a=/=b , this will output z for z. What should I write if a=/=b, it will do " if (b==c) z=b; Click to expand...

Advanced Member level 3

Your always_comb blocks is not combinatorial - if a != b, and b != c, then there is no assignment to z and you have a latch. Your second if statement needs an else clause. In any case, the conditional ?: operator can be nested: assign z = (a==b) ? a : (b==c) ? b : z; That z at the end represents the missing else clause.  

Full Member level 6

Advanced Member level 5

always_comb is the same function as assign Click to expand...

if(a==b) begin z=a; count=count+1; end else if (b==c) begin z=b; count=count+2; end Click to expand...

assign z = (a==b) ? (a & (count=count+1)) : (b==c) ?( b & (count=count+2)): z; Click to expand...

daisordan, If you want your code to be synthesizable, you cannot combine combinatorial and sequential logic like this in a single assign statement. You will need to explain your desired functionality without using any Verilog syntax first so we can suggest the best way to code what you want to achieve. If you don't care if your code is synthesizable, you can assign the output of a function call Code: assign z = myfunction(a,b,c); function logic myfunction(input a,b,c); if(a==b) begin z=a; count=count+1; // this is a side-effect that is not synthesizable end else if (b==c) begin z=b; count=count+2; // this is a side-effect that is not synthesizable end endfunction The biggest difference between always_comb and an assign statement is with the how the simulator deals with the semantics of function calls. An assignment statement only looks for events on the operands that appear on the RHS of the assignment, while always_comb expands functions in-line and looks for any change of any operand that appears inside the function. For example suppose I re-wrote the function to directly reference a,b,c instead of passing them as arguments to the function: Code: assign z1 = myfunction(); always_comb z2 = myfunction(); function logic myfunction(); if(a==b) z=a; else if (b==c) z=b; else z ='bx; // a don't care to prevent a latch endfunction The asssign z1= statement would never execute because there are no triggering events on the RHS to cause an evaluation. The always_comb z2= block executes at time 0, and when there is a change on any operand that is referenced within the block. mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like Code: real pi; `define PI 3.14159 always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead that fails because there was never an event to trigger the always @(*) block.  

daisordan said: mrflibble: Could you briefly talk about why always_comb and assign are different? because when I read some verilog beginner's book, it said that are doing the same things. Click to expand...

dave_59 said: mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like Code: real pi; `define PI 3.14159 always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead that fails because there was never an event to trigger the always @(*) block. Click to expand...

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How does Verilog treat multiple if blocks inside always_ff

If I have two if statements inside an always_ff block, such as:

If x=6, which means both conditions are satisfied, will both if blocks get executed, or only the first one?

• 3 \$\begingroup\$ Both get "executed". Remember, this is HDL, so both get "activated" in parallel. If they both assign to the same signal(s), the last assignment in the block will prevail. \$\endgroup\$ –  Dave Tweed Commented Feb 13, 2022 at 4:32

2 Answers 2

All code within a begin / end block gets executed consecutively. When the first if condition is true , the statements inside the next begin / end block get executed consecutively. Then when the the second if condition is true , the statements inside the next begin / end block get executed consecutively.

When both conditions are true, you will have two sets of statement blocks executing consecutively. If your intent is to have only one block execute, then you should be using the else clause.

• \$\begingroup\$ With the clarification that the signals as seen from outside the block that are given new values inside the various if statements will not change more than once in a simulation cycle. The notion of consecutive execution applies only inside the always block. \$\endgroup\$ –  Elliot Alderson Commented Feb 13, 2022 at 12:19

There are 2 possible conditions here: 1) We are allocating values to the same register in both if conditions; 2) We are allocating values to different registers in the two if conditions.

If we are dealing with condition #1, i.e., allocating values to the same register (lets say "z") then: The second if condition would run as follows: The final value of "z" would be "2" after the clk posedge..

If we dealing with condition #2, i.e., allocating values to different registers in the two if conditions, then both if conditions would run as follows: We would have values for y = 1 and z = 2 after the clk posedge.

The rules for all Verilog behavior are set in the IEEE Std 1800-2017. Section 9.3.1 Sequential blocks, states:

A sequential block shall have the following characteristics: — Statements shall be executed in sequence, one after another.

In this context, a sequential block is defined by the begin/end keywords.

Also, section 10.4.2 Nonblocking procedural assignments:

The order of the execution of distinct nonblocking assignments to a given variable shall be preserved.

• \$\begingroup\$ The first one will also run, though. You don't say that it won't, but it's unclear. \$\endgroup\$ –  Hearth Commented Oct 17, 2023 at 1:21
• \$\begingroup\$ @Hearth yes you are right if we are allocating values to different register. Thanks for making that clear, I'll edit my answer. \$\endgroup\$ –  AZ123 Commented Oct 17, 2023 at 12:34

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Nested conditional operator / mux syntax

I am trying to output a tone to a speaker via a set of pushbuttons. I managed to make it work with a case statement but am having trouble trying translating that to a mux, as case statements within always_ff are not allowed according my guidelines. I keep getting an error for Procedural continuous assignment error and I'm not sure on the meaning of that

My code is as follows

• system-verilog

• Sorry I meant I made the circuit work with a case statement, syntax wise. But project parameter wise, I am not allowed to use case or if statements within an always_ff block. Therefore I have to convert the case statement to a mux or something else in order to fulfill the requirements –  JohnRambo Commented Feb 11, 2021 at 19:42

2 Answers 2

A procedural continuous assignment is an assign statement inside an always block, initial block, or other procedural block. They have limited if any support synthesis support. Most simulators support this feature, however the SystemVerilog LRM has been warning about deprecating the feature since IEEE1800-2005 (you can read about the explanation in IEEE1800-2017 § C.4.2).

Once a procedural block reaches the assign statement, the line will be treated as a continuous assignment until a different assign or deassign on the same variable is executed. In your case count will be updated on any change of x or count (asynchronous feedback loop). It will consider clk50 for its first posedge only to trigger the procedural continuous assignment. After that time the clock is ignored

You should avoid using assign (and deassign ) inside procedural code. You should also use non-blocking assignments ( <= ) when assigning synchronous logic to avoid simulation race conditions. Change your assignment to count to the follow to get the desired behavior:

References and examples of procedural continuous assignment in the latest SystemVerilog RLM IEEE Std 1800-2017 :

• § 10.6.1 The assign and deassign procedural statements
• § C.4 Constructs identified for deprecation
• § C.4.2 Procedural assign and deassign statements

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